1. Field of the Invention
The present invention relates to testing of integrated circuits and more particularly relates to built-in self test arrangements that are provided on the integrated circuit chip itself.
2. Background Art
As the integrated circuit art has advanced, more and more circuit devices, and consequently more and more circuit function, have been placed on single chips. These developments have posed problems with regard to the testing of such circuits. For example, while the testing of even an extremely large memory array chip may be relatively straight forward, a chip that integrates various different kinds of functions, including an embedded memory array and logic, may pose problems for the circuit designer/tester who desires adequate testability of the embedded memory array. For example, typically such embedded memory arrays have far fewer I/O pins available to the circuit tester than a memory array occupying a stand alone chip. The problems associated with testing of embedded memory arrays extend to embedded logic function as well.
A general solution to the above-described problems that have developed is to embed test circuitry on the chip itself. Such schemes are frequently referred to as Built-In Self Test ("BIST") or Array Self Test ("AST"). Hereinafter, such arrangements are referred to generically as BIST circuits. In the case of testing embedded memory circuits, such as Static Random Access Memory Circuits and Dynamic Random Access Memory Circuits, BIST circuits have heretofore been limited to the provision of deterministic patterns by way of memory arrays that take large amounts of chip area, which is undesirable.
For background, please refer to "A Realistic Self-Test Machine For Static Random Access Memories," by R. Dekker, F. Beenker, L. Thijssen, 1988 IEEE International Test Conference, pp. 353-361; "A 55 ns 16 Mb Dram," by T. Takeshima, et al., 1989 IEEE International Solid States Circuits Conference, Digest Of Technical Papers, pp. 246 et seq.; "RPST: A ROM based Pseudo-Exhaustive Self-Test Approach," by M. Ligthart, et al., 1987 IEEE International Test Conference, pp. 915 et seq., "An Efficient Built-In Self-Testing For Random Access Memory," by P. Mazumder and J. Patel, 1987 IEEE International Test Conference, pp. 1072 et seq.; and "A Novel Approach For Testing Memories Using A Built-In Self-Testing Technique," by K. Le and K. Saluja, 1986 IEEE International Test Conference, pp. 830 et seq.
Another characteristic of prior art BIST circuits is that such circuits typically default to a wait state after completing its pattern set. This operation has actually been considered to be desirable, as it preserves result data valid upon completion of the test.
U.S. Pat. No. 4,740,970, issued Apr. 26, 1988, discloses a built-in logic block observation ("BILBO") register design, whereby register elements are adapted to operate selectively in different operating modes in response to control signals from control means.
U.S. Pat. No. 4,788,684, issued Nov. 29, 1988, discloses a memory test apparatus comprising means for generating an algorithmic pattern to be provided as input to the memory under test. An auxilliary pattern generator is used for storing expected values of the memory under test, against which the memory output is compared.
U.S. Pat. No. 4,984,800, issued Jan. 16, 1990, discloses a reconfigurable register bit-slice for use in BILBO circuits. Front end logic is disclosed which switches a single circuit switch between a data input and an output of the front end logic. Thus, a single circuit switch of delay is added to normal operation of a standard shift register, modified to be reconfigurable.
U.S. Pat. No. 4,404,519, issued Sep. 13, 1983, discloses test circuitry for embedded arrays which is not directly accessible from primary input/output pins. This test circuitry, which is manufactured directly on chip, permits external testers to invoke a variety of array tests without redesigning the chip architecture.
U.S. Pat. No. 4,667,330, issued May 19, 1987, discloses a semiconductor memory chip with self-diagnostic means which functions to indicate a defective cell. The self-diagnostic circuitry is mounted on the same chip as that of the memory array and has means for storing information to be stored in the memory array, and means for comparing the content of said storing means with output information which is read out of the address at which the information is stored.
U.S. Pat. No. 4,635,261, issued Jan. 6, 1987, discloses an on-chip test system for arrays which allows both synchronous and pipeline modes of normal operation. Control logic is coupled between control signal inputs and shift registers for selecting the system's mode of operation. A comparatory circuit is coupled to output shift registers for comparing system output signals with expected signals.
U.S. Pat. No. 4,357,703, issued Nov. 2, 1982, discloses a test system for LSI circuits resident on each LSI chip under test. The test system provides test operands for the logic function under test and analyzes the resulting operands. Checksum logic together with a shift register produce a running checksum of all output states of the module under test at the operative clock rate of the LSI.